The purpose of semiconductor chip packaging is to protect the chip itself and to interconnect the signals between chips. For a long time in the past, the improvement of chip performance mainly relied on the improvement of design and manufacturing process.
However, as the transistor structure of semiconductor chips entered the FinFET era, the progress of the process node showed a significant slowdown in the situation. Although according to the industry’s development roadmap, there is still a lot of room for the process node iteration to rise, we can clearly feel the slowdown of Moore’s Law, as well as the pressure brought about by the surge in production costs.
As a result, it has become a very important means to further explore the potential for performance improvement by reforming packaging technology. A few years ago, the industry has emerged through the technology of advanced packaging to realize the slogan “beyond Moore (More than Moore)”!
The so-called advanced packaging, the general industry’s common definition is: all the use of front-channel manufacturing process methods of packaging technology
By means of advanced packaging, we can:
1. Significantly reduce the area of the chip after packaging
Whether it is a combination of multiple chips, or a single chip Wafer Levelization package, can significantly reduce the size of the package in order to reduce the use of the entire system board area. The use of packaging means to reduce the chip area in the economy than to enhance the front-end process to be more cost-effective.
2. Accommodate more chip I/O ports
Due to the introduction of the front-end process, we can utilize RDL technology to accommodate more I/O pins per unit area of the chip, thus reducing the waste of chip area.
3. Reduce the overall manufacturing cost of the chip
Due to the introduction of Chiplet, we can easily combine multiple chips with different functions and process technologies/nodes to form a system-in-package (SIP). This avoids the costly approach of having to use the same (highest process) for all functions and IPs.
4. Enhance interconnectivity between chips
As the demand for large computing power increases, in many application scenarios it is necessary for the computing unit (CPU, GPU…) and DRAM to do a lot of data exchange. This often leads to almost half of the performance and power consumption of the whole system being wasted on information interaction. Now that we can reduce this loss to less than 20% by connecting the processor and DRAM as close together as possible through various 2.5D/3D packages, we can dramatically reduce the cost of computing. This increase in efficiency far outweighs the advances made through the adoption of more advanced manufacturing processes
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Post time: Sep-22-2023