Should the AGND and DGND ground layers be separated?
The simple answer is that it depends on the situation, and the detailed answer is that they are usually not separated. Because in most cases, separating the ground layer will only increase the inductance of the return current, which brings more harm than good. The formula V = L(di/dt) shows that as the inductance increases, the voltage noise increases. And as the switching current increases (because the converter sampling rate increases), the voltage noise will also increase. Therefore, the grounding layers should be connected together.
An example is that in some applications, in order to comply with traditional design requirements, dirty bus power or digital circuitry must be placed in certain areas, but also by the size constraints, making the board can not achieve a good layout partition, in this case, separate grounding layer is the key to achieve good performance. However, in order for the overall design to be effective, these grounding layers must be connected together somewhere on the board by a bridge or connection point. Therefore, the connection points should be evenly distributed across the separated grounding layers. Ultimately, there will often be a connection point on the PCB that becomes the best location for returning current to pass through without causing degradation in performance. This connection point is usually located near or below the converter.
When designing the power supply layers, use all the copper traces available for these layers. If possible, do not allow these layers to share alignments, as additional alignments and vias can quickly damage the power supply layer by splitting it into smaller pieces. The resulting sparse power layer can squeeze the current paths to where they are most needed, namely the power pins of the converter. Squeezing the current between the vias and the alignments raises the resistance, causing a slight voltage drop across the converter’s power pins.
Finally, power supply layer placement is critical. Never stack a noisy digital power supply layer on top of an analog power supply layer, or the two may still couple even though they are on different layers. To minimize the risk of system performance degradation, the design should separate these types of layers rather than stacking them together whenever possible.
Can a PCB’s power delivery system (PDS) design be ignored?
The design goal of a PDS is to minimize the voltage ripple generated in response to power supply current demand. All circuits require current, some with high demand and others that require current to be supplied at a faster rate. Using a fully decoupled low-impedance power or ground layer and a good PCB lamination minimizes the voltage ripple due to the current demand of the circuit. For example, if the design is designed for a switching current of 1A and the impedance of the PDS is 10mΩ, the maximum voltage ripple is 10mV.
First, a PCB stack structure should be designed to support larger layers of capacitance. For example, a six-layer stack might contain a top signal layer, a first ground layer, a first power layer, a second power layer, a second ground layer, and a bottom signal layer. The first ground layer and the first power supply layer are provided to be in close proximity to each other in the stacked structure, and these two layers are spaced 2 to 3 mils apart to form an intrinsic layer capacitance. The great advantage of this capacitor is that it is free and only needs to be specified in the PCB manufacturing notes. If the power supply layer must be split and there are multiple VDD power rails on the same layer, the largest possible power supply layer should be used. Do not leave empty holes, but also pay attention to sensitive circuits. This will maximize the capacitance of that VDD layer. If the design allows for the presence of additional layers, two additional grounding layers should be placed between the first and second power supply layers. In the case of the same core spacing of 2 to 3 mils, the inherent capacitance of the laminated structure will be doubled at this time.
For ideal PCB lamination, decoupling capacitors should be used at the starting entry point of the power supply layer and around the DUT, which will ensure that the PDS impedance is low over the entire frequency range. Using a number of 0.001µF to 100µF capacitors will help cover this range. It is not necessary to have capacitors everywhere; docking capacitors directly against the DUT will break all manufacturing rules. If such severe measures are needed, the circuit has other problems.
The Importance of Exposed Pads (E-Pad)
This is an easy aspect to overlook, but it is critical to achieving the best performance and heat dissipation of the PCB design.
Exposed pad (Pin 0) refers to a pad underneath most modern high-speed ICs, and it is an important connection through which all internal grounding of the chip is connected to a central point underneath the device. The presence of an exposed pad allows many converters and amplifiers to eliminate the need for a ground pin. The key is to form a stable and reliable electrical connection and thermal connection when soldering this pad to the PCB, otherwise the system could be severely damaged.
Optimal electrical and thermal connections for exposed pads can be achieved by following three steps. First, where possible, the exposed pads should be replicated on each PCB layer, which will provide a thicker thermal connection for all ground and thus fast heat dissipation, especially important for high power devices. On the electrical side, this will provide a good equipotential connection for all grounding layers. When replicating the exposed pads on the bottom layer, it can be used as a decoupling ground point and a place to mount heat sinks.
Next, split the exposed pads into multiple identical sections. A checkerboard shape is best and can be achieved by screen cross grids or solder masks. During reflow assembly, it is not possible to determine how the solder paste flows to establish the connection between the device and the PCB, so the connection may be present but unevenly distributed, or worse, the connection is small and located at the corner. Dividing the exposed pad into smaller sections allows each area to have a connection point, thus ensuring a reliable, even connection between the device and the PCB.
Finally, it should be ensured that each section has an over-hole connection to ground. The areas are usually large enough to hold multiple vias. Before assembly, be sure to fill each vias with solder paste or epoxy. This step is important to ensure that the exposed pad solder paste does not flow back into the vias cavities, which would otherwise reduce the chances of a proper connection.
The problem of cross-coupling between the layers in the PCB
In PCB design, the layout wiring of some high-speed converters will inevitably have one circuit layer cross-coupled with another. In some cases, the sensitive analog layer (power, ground, or signal) may be directly above the high-noise digital layer. Most designers think this is irrelevant because these layers are located on different layers. Is this the case? Let’s look at a simple test.
Select one of the adjacent layers and inject a signal at that level, then, connect the cross-coupled layers to a spectrum analyzer. As you can see, there are very many signals coupled to the adjacent layer. Even with a spacing of 40 mils, there is a sense in which the adjacent layers still form a capacitance, so that at some frequencies the signal will still be coupled from one layer to another.
Assuming a high noise digital part on a layer has a 1V signal from a high speed switch, the non-driven layer will see a 1mV signal coupled from the driven layer when the isolation between layers is 60dB. For a 12-bit analog-to-digital converter (ADC) with a 2Vp-p full-scale swing, this means 2LSB (least significant bit) of coupling. For a given system, this may not be a problem, but it should be noted that when the resolution is increased from 12 to 14 bits, the sensitivity increases by a factor of four and thus the error increases to 8LSB.
Ignoring cross-plane/cross-layer coupling may not cause the system design to fail, or weaken the design, but one must remain vigilant, as there may be more coupling between the two layers than one might expect.
This should be noted when noise spurious coupling is found within the target spectrum. Sometimes layout wiring can lead to unintended signals or layer cross-coupling to different layers. Keep this in mind when debugging sensitive systems: the problem may lie in the layer below.
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Post time: Apr-27-2022